1. Field of the Invention
The present invention relates to a junction short-circuiting-type programmable read-only memory (PROM) device in which bipolar transistor technology is used.
2. Description of the Prior Art
In a general junction short-circuiting-type PROM device, a memory cell, which has the same structure as a conventional bipolar transistor, is located at each intersection of the word lines and bit lines. That is, one memory cell has a collector connected to one of the word lines, an emitter connected to one of the bit lines, and a floating-state base. When the memory cell is of the NPN type, the write-in operation for this memory cell is performed by supplying an excess current from the emitter to the collector so as to break down or short-circuit the PN junction between the emitter and the base. Therefore, the written-in memory cell serves as a diode.
According to the structure of a first prior art PROM device, a plurality of base regions are disposed within one collector region corresponding to one word line, and, in addition, one emitter region corresponding to one bit line is disposed within each base region. In this structure, however, one collector electrode is disposed for every four to eight base regions, that is, for every four to eight memory cells, and the write-in current fluctuates in accordance with the location of the cell, thereby causing an increase of the write-in current, which also causes the peripheral circuits to be complex. In addition, the resistance between the emitter and collector of a memory cell also fluctuates in accordance with the location of the cell. Therefore, in order to avoid an increase of the resistance between the emitter and collector of a memory cell, the size of the memory cell must be increased, thereby reducing integration.
According to the structure of a second prior art PROM device (see Japanese Unexamined Patent Publication (Kokai) No. 55-55561), the write-in current does not fluctuate in accordance with the location of the memory cell. That is, in this structure, disposed in a collector region are a collector electrode and two base regions on both sides thereof. In other words, two memory cells are formed in individual collector regions. In this structure, however, as compared with the first prior art PROM, the manufacturing yield is reduced, and, in addition, integration is reduced. Further, the access speed, which will be explained later, is reduced.